1. Field of the Invention
The present invention generally relates to performance optimization for processor-based devices, and more particularly to adaptive performance optimization for a processor-based device.
2. Description of the Related Art
Most processor-based devices today are equipped with performance monitoring counters, also termed programmable event counters. These counters permit processor performance parameters to be monitored and measured. One current performance monitoring technique utilizes two performance monitoring counters which simultaneously record the occurrence of pre-specified events. When one of the counters overflows, counting stops and an interrupt is generated. A software interrupt handler records the counter values. Post-processing software is used to analyze the gathered data. Based on the observed conditions, the processor-based device optimizes its performance by dynamically changing operating parameters.
A similar performance monitoring technique utilizes multiple programmable event counters to monitor multiple events. The counters typically operate synchronously, are non-intrusive to the operation of the processor, and are externally accessible through a standard Joint Test Action Group (JTAG) interface. An event select register has been used to control the programmable event counters. Examples of processor performance parameters typically measure typically by programmable event counters are cache hits, cache snoops, data reads, data writes, branches, pipeline flushes, executed instructions, locked bus cycles, hardware interrupts, bank conflicts, and I/O cycles.
A significant concern with the above performance monitoring techniques is counter overflow. Counter overflow has typically been addressed through use of larger counters. By increasing the size of a counter, interrupts are generated less frequently. This is desirable since interrupts intrude into normal processor operation. On the other hand, large counters result in greater data averaging. Data averaging is undesirable because data averaging prevents observation of temporary fluctuations in performance parameters. Increasing the size of a counter also increases implementation costs. Thus, varying the size of performance monitoring counters has been a tradeoff. What is needed is a performance monitoring device that does not require a tradeoff as described above.
Briefly in accordance with the present invention, a processor-based device supports performance optimization with use of an adaptive digital element. The adaptive digital element generates probability data corresponding to a probability of a performance parameter of the processor-based device. The probability data is repeatedly compared to input data corresponding to the performance parameter and adapted to match the input data. After a predetermined number of samples, a probability value corresponding to the probability data aid stored in a counter of the adaptive digital element converges to a good estimated probability of the performance parameter. The probability value is then detected, and the processor-based device is adapted in accordance with the probability value. A processor of the processor-based device also can adapt system operation when the probability value reaches a predetermined trigger value. One advantage of this overall technique is that it essentially eliminates any prospect of counter overflow aid associated interrupt processing. Also, the device can accommodate multiple performance parameters by selecting a particular performance parameter for measurement by the adaptive digital element.